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19-2600; Rev 0; 9/02
Dual 8-Bit, 40Msps, 3V, Low-Power ADC with Internal Reference and Multiplexed Parallel Outputs
General Description
The MAX1196 is a 3V, dual 8-bit analog-to-digital converter (ADC) featuring fully differential wideband trackand-hold (T/H) inputs, driving two ADCs. The MAX1196 is optimized for low power, small size, and high-dynamic performance for applications in imaging, instrumentation, and digital communications. This ADC operates from a single 2.7V to 3.6V supply, consuming only 87mW while delivering a typical signal-to-noise and distortion (SINAD) of 48.4dB at an input frequency of 20MHz and a sampling rate of 40Msps. The T/H driven input stages incorporate 400MHz (-3dB) input amplifiers. The converters can also be operated with singleended inputs. In addition to low operating power, the MAX1196 features a 3mA sleep mode as well as a 0.1A power-down mode to conserve power during idle periods. An internal 2.048V precision bandgap reference sets the full-scale range of the ADC. A flexible reference structure allows the use of this internal or an externally applied reference, if desired for applications requiring increased accuracy or a different input voltage range. The MAX1196 features parallel, multiplexed, CMOScompatible three-state outputs. The digital output format can be set to two's complement or straight offset binary through a single control pin. The device provides for a separate output power supply of 1.7V to 3.6V for flexible interfacing. The MAX1196 is available in a 7mm x 7mm, 48-pin TQFP package, and is specified for the extended industrial (-40C to +85C) temperature range. Pin-compatible, nonmultiplexed higher speed versions of the MAX1196 are also available. Refer to the MAX1198 data sheet for 100Msps, the MAX1197 data sheet for 60Msps, and the MAX1195 data sheet for 40Msps. For a 10-bit, pin-compatible upgrade, refer to the MAX1186 data sheet. With the N.C. pins of the MAX1196 internally pulled down to ground, this ADC becomes a drop-in replacement for the MAX1186. o Single 2.7V to 3.6V Operation o Excellent Dynamic Performance 48.4dB/44.7dB SINAD at fIN = 20MHz/200MHz 68.9dB/53dBc SFDR at fIN = 20MHz/200MHz o -72dB Interchannel Crosstalk at fIN = 20MHz o Low Power 87mW (Normal Operation) 9mW (Sleep Mode) 0.3W (Shutdown Mode) o 0.05dB Gain and 0.05 Phase Matching o Wide 1VP-P Differential Analog Input Voltage Range o 400MHz -3dB Input Bandwidth o On-Chip 2.048V Precision Bandgap Reference o User-Selectable Output Format--Two's Complement or Offset Binary o Pin-Compatible 8-Bit and 10-Bit Upgrades Available
Features
MAX1196
Ordering Information
PART TEMP RANGE MAX1196ECM -40C to +85C *EP = Exposed pad. PIN-PACKAGE 48 TQFP-EP*
Pin Configuration
REFN REFP REFIN REFOUT D7A/B D6A/B D5A/B D4A/B D3A/B D2A/B D1A/B D0A/B
48 47 46 45 44 43 42 41 40 39 38
COM VDD GND INA+ INAVDD GND INBINB+ GND VDD CLK
37
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
36 35 34 33 32 31 30 29 28 27 26 25
N.C. N.C. OGND OVDD OVDD OGND A/B N.C. N.C. N.C. N.C. N.C.
Applications
Baseband I/Q Sampling Multichannel IF Sampling Ultrasound and Medical Imaging Battery-Powered Instrumentation WLAN, WWAN, WLL, MMDS Modems Set-Top Boxes VSAT Terminals
Functional Diagram appears at end of data sheet.
MAX1196
________________________________________________________________ Maxim Integrated Products
GND VDD VDD GND T/B SLEEP PD OE N.C. N.C. N.C. N.C.
TQFP-EP
1
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Dual 8-Bit, 40Msps, 3V, Low-Power ADC with Internal Reference and Multiplexed Parallel Outputs MAX1196
ABSOLUTE MAXIMUM RATINGS
VDD, OVDD to GND .............................................. -0.3V to +3.6V OGND to GND...................................................... -0.3V to +0.3V INA+, INA-, INB+, INB- to GND ...............................-0.3V to VDD REFIN, REFOUT, REFP, REFN, COM, CLK to GND............................................-0.3V to (VDD + 0.3V) OE, PD, SLEEP, T/B, D7A/B-D0A/B, A/B to OGND...............-0.3V to (OVDD + 0.3V) Continuous Power Dissipation (TA = +70C) 48-Pin TQFP (derate 12.5mW/C above +70C)........1000mW Operating Temperature Range ...........................-40C to +85C Junction Temperature ......................................................+150C Storage Temperature Range .............................-60C to +150C Lead Temperature (soldering, 10s) .................................+300C
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(VDD = OVDD = 3V, 0.1F and 2.2F capacitors from REFP, REFN, and COM to GND; REFOUT connected to REFIN through a 10k resistor, VIN = 2VP-P (differential with respect to COM), CL = 10pF at digital outputs (Note 5), fCLK = 40MHz, TA = TMIN to TMAX, unless otherwise noted. +25C guaranteed by production test, <+25C guaranteed by design and characterization. Typical values are at TA = +25C.)
PARAMETER DC ACCURACY Resolution Integral Nonlinearity Differential Nonlinearity Offset Error Gain Error Gain Temperature Coefficient ANALOG INPUT Differential Input Voltage Range Common-Mode Input Voltage Range Input Resistance Input Capacitance CONVERSION RATE Maximum Clock Frequency Data Latency DYNAMIC CHARACTERISTICS (fCLK = 40MHz) fINA or B = 2MHz at -1dB FS Signal-to-Noise Ratio SNR fINA or B = 7.5MHz at -1dB FS fINA or B = 20MHz at -1dB FS fINA or B = 101MHz at -1dB FS fINA or B = 2MHz at -1dB FS Signal-to-Noise and Distortion SINAD fINA or B = 7.5MHz at -1dB FS fINA or B = 20MHz at -1dB FS fINA or B = 101MHz at -1dB FS 47 47.5 48.7 48.7 48.5 48 48.6 48.7 48.4 48 dB dB fCLK CHA CHB 40 5 5.5 MHz Clock Cycles VDIFF VCM RIN CIN Switched capacitor load Differential or single-ended inputs 100 1.0 VDD / 2 0.2 140 5 INL DNL fIN = 7.51MHz (Note 1) fIN = 7.51MHz, no missing codes guaranteed (Note 1) SYMBOL CONDITIONS MIN 8 0.3 0.15 1 1 4 4 TYP MAX UNITS Bits LSB LSB %FS %FS ppm/C V V k pF
2
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Dual 8-Bit, 40Msps, 3V, Low-Power ADC with Internal Reference and Multiplexed Parallel Outputs
ELECTRICAL CHARACTERISTICS (continued)
(VDD = OVDD = 3V, 0.1F and 2.2F capacitors from REFP, REFN, and COM to GND; REFOUT connected to REFIN through a 10k resistor, VIN = 2VP-P (differential with respect to COM), CL = 10pF at digital outputs (Note 5), fCLK = 40MHz, TA = TMIN to TMAX, unless otherwise noted. +25C guaranteed by production test, <+25C guaranteed by design and characterization. Typical values are at TA = +25C.)
PARAMETER SYMBOL CONDITIONS fINA or B = 2MHz at -1dB FS Spurious-Free Dynamic Range SFDR fINA or B = 7.5MHz at -1dB FS fINA or B = 20MHz at -1dB FS fINA or B = 101MHz at -1dB FS fINA or B = 2MHz at -1dB FS Third-Harmonic Distortion HD3 fINA or B = 7.5MHz at -1dB FS fINA or B = 20MHz at -1dB FS fINA or B = 101MHz at -1dB FS Intermodulation Distortion (First Five Odd-Order IMDs) (Note 2) Third-Order Intermodulation Distortion (Note 2) IMD IM3 fIN1(A or B) = 1.997MHz at -7dB FS, fIN2(A or B) = 2.046MHz at -7dB FS fIN1(A or B) = 1.997MHz at -7dB FS, fIN2(A or B) = 2.046MHz at -7dB FS fINA or B = 2MHz at -1dB FS Total Harmonic Distortion (First Four Harmonics) Small-Signal Bandwidth Full-Power Bandwidth Gain Flatness (12MHz Spacing) (Note 3) Aperture Delay Aperture Jitter Overdrive Recovery Time tAD tAJ 1dB SNR degradation at Nyquist For 1.5 x full-scale input FPBW THD fINA or B = 7.5MHz at -1dB FS fINA or B = 20MHz at -1dB FS fINA or B = 101MHz at -1dB FS Input at -20dB FS, differential inputs Input at -1dB FS, differential inputs fIN1(A or B) = 106MHz at -1dB FS, fIN2(A or B) = 118MHz at -1dB FS 60 MIN TYP 69 70 68.9 65 -72 -73.7 -75 -67 -68 -73.2 -70 -69 -69 -63 500 400 0.05 1 2 2 2.048 3% 2.012 0.988 VDD / 2 0.1 1.024 3% 100 MHz MHz dB ns psRMS ns -57 dBc dBc dBc dBc dBc MAX UNITS
MAX1196
INTERNAL REFERENCE (REFIN = REFOUT through 10k resistor; REFP, REFN, and COM levels are generated internally.) Reference Output Voltage Positive Reference Output Voltage Negative Reference Output Voltage Common-Mode Level Differential Reference Output Voltage Range Reference Temperature Coefficient VREFOUT VREFP VREFN VCOM VREF TCREF (Note 4) (Note 5) (Note 5) (Note 5) VREF = VREFP - VREFN V V V V V ppm/C
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3
Dual 8-Bit, 40Msps, 3V, Low-Power ADC with Internal Reference and Multiplexed Parallel Outputs MAX1196
ELECTRICAL CHARACTERISTICS (continued)
(VDD = OVDD = 3V, 0.1F and 2.2F capacitors from REFP, REFN, and COM to GND; REFOUT connected to REFIN through a 10k resistor, VIN = 2VP-P (differential with respect to COM), CL = 10pF at digital outputs (Note 5), fCLK = 40MHz, TA = TMIN to TMAX, unless otherwise noted. +25C guaranteed by production test, <+25C guaranteed by design and characterization. Typical values are at TA = +25C.)
PARAMETER Positive Reference Output Voltage Negative Reference Output Voltage Common-Mode Level Differential Reference Output Voltage Range REFIN Resistance Maximum REFP, COM Source Current Maximum REFP, COM Sink Current Maximum REFN Source Current Maximum REFN Sink Current SYMBOL CONDITIONS MIN TYP MAX UNITS
BUFFERED EXTERNAL REFERENCE (VREFIN = 2.048V) VREFP VREFN VCOM VREF RREFIN ISOURCE ISINK ISOURCE ISINK RREFP, RREFN CIN VREF VCOM VREFP VREFN VREF = VREFP - VREFN (Note 5) (Note 5) (Note 5) VREF = VREFP - VREFN 2.012 0.988 VDD / 2 0.1 1.024 2% >50 5 -250 250 -5 V V V V M mA A A mA
UNBUFFERED EXTERNAL REFERENCE (VREFIN = AGND, reference voltage applied to REFP, REFN, and COM) REFP, REFN Input Resistance REFP, REFN, COM Input Capacitance Differential Reference Input Voltage Range COM Input Voltage Range REFP Input Voltage REFN Input Voltage Measured between REFP and REFN 4 15 1.024 10% VDD / 2 5% VCOM + VREF / 2 VCOM VREF / 2 0.8 x VDD 0.8 x OVDD 0.2 x VDD 0.2 x OVDD k pF V V V V
DIGITAL INPUTS (CLK, PD, OE, SLEEP, T/B) CLK Input High Threshold VIH PD, OE, SLEEP, T/B CLK Input Low Threshold VIL PD, OE, SLEEP, T/B
V
V
4
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Dual 8-Bit, 40Msps, 3V, Low-Power ADC with Internal Reference and Multiplexed Parallel Outputs
ELECTRICAL CHARACTERISTICS (continued)
(VDD = OVDD = 3V, 0.1F and 2.2F capacitors from REFP, REFN, and COM to GND; REFOUT connected to REFIN through a 10k resistor, VIN = 2VP-P (differential with respect to COM), CL = 10pF at digital outputs (Note 5), fCLK = 40MHz, TA = TMIN to TMAX, unless otherwise noted. +25C guaranteed by production test, <+25C guaranteed by design and characterization. Typical values are at TA = +25C.)
PARAMETER Input Hysteresis Input Leakage Input Capacitance Output Voltage Low Output Voltage High Three-State Leakage Current Three-State Output Capacitance POWER REQUIREMENTS Analog Supply Voltage Range Output Supply Voltage Range VDD OVDD Operating, fINA&B = 20MHz at -1dB FS applied to both channels Analog Supply Current IVDD Sleep mode Shutdown, clock idle, PD = OE = OVDD Operating, fINA&B = 20MHz at -1dB FS applied to both channels (Note 6) Output Supply Current IOVDD Sleep mode Shutdown, clock idle, PD = OE = OVDD Operating, fINA&B = 20MHz at -1dB FS applied to both channels Analog Power Dissipation PDISS Sleep mode Shutdown, clock idle, PD = OE = OVDD Power-Supply Rejection TIMING CHARACTERISTICS CLK Rise to CHA Output Data Valid CLK Fall to CHB Output Data Valid Clock Rise/Fall to A/B Rise/Fall Time OE Fall to Output Enable Time OE Rise to Output Disable Time CLK Pulse Width High tDOA tDOB tDA/B tENABLE tDISABLE tCH Clock period: 25ns (Note 7) CL = 20pF (Notes 1, 7) CL = 20pF (Notes 1, 7) 6 6 6 5 5 12.5 1.5 8.25 8.25 ns ns ns ns ns ns PSRR Offset, VDD 5% Gain, VDD 5% 2.7 1.7 3 3 29 3 0.1 8 3 3 87 9 0.3 3 3 60 W mV/V 10 108 20 A mA A 3.6 3.6 36 V V mA SYMBOL VHYST IIH IIL CIN VOL VOH ILEAK COUT ISINK = -200A ISOURCE = 200A OE = OVDD OE = OVDD 5 OVDD 0.2 10 VIH = VDD = OVDD VIL = 0 5 0.2 CONDITIONS MIN TYP 0.15 20 20 MAX UNITS V A pF V V A pF
MAX1196
DIGITAL OUTPUTS (D0A/B-D7A/B, A/B)
mW
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5
Dual 8-Bit, 40Msps, 3V, Low-Power ADC with Internal Reference and Multiplexed Parallel Outputs MAX1196
ELECTRICAL CHARACTERISTICS (continued)
(VDD = OVDD = 3V, 0.1F and 2.2F capacitors from REFP, REFN, and COM to GND; REFOUT connected to REFIN through a 10k resistor, VIN = 2VP-P (differential with respect to COM), CL = 10pF at digital outputs (Note 5), fCLK = 40MHz, TA = TMIN to TMAX, unless otherwise noted. +25C guaranteed by production test, <+25C guaranteed by design and characterization. Typical values are at TA = +25C.)
PARAMETER CLK Pulse Width Low Wake-Up Time SYMBOL tCL tWAKE CONDITIONS Clock period: 25ns (Note 7) Wake-up from sleep mode Wake-up from shutdown mode (Note 8) fINA or B = 20MHz at -1dB FS (Note 9) fINA or B = 20MHz at -1dB FS (Note 10) fINA or B = 20MHz at -1dB FS (Note 11) MIN TYP 12.5 1.5 1 20 -72 0.05 0.05 MAX UNITS ns s
CHANNEL-TO-CHANNEL MATCHING Crosstalk Gain Matching Phase Matching
dB dB Degrees
Note 1: Guaranteed by design. Not subject to production testing. Note 2: Intermodulation distortion is the total power of the intermodulation products relative to the total input power. Note 3: Analog attenuation is defined as the amount of attenuation of the fundamental bin from a converted FFT between two applied input signals with the same magnitude (peak-to-peak) at fIN1 and fIN2. Note 4: REFIN and REFOUT should be bypassed to GND with a 0.1F (min) and 2.2F (typ) capacitor. Note 5: REFP, REFN, and COM should be bypassed to GND with a 0.1F (min) and 2.2F (typ) capacitor. Note 6: Typical digital output current at fINA&B = 20MHz. For digital output currents vs. analog input frequency, see the Typical Operating Characteristics. Note 7: See Figure 3 for detailed system timing diagrams. Clock to data valid timing is measured from 50% of the clock level to 50% of the data output level. Note 8: SINAD settles to within 0.5dB of its typical value in unbuffered external reference mode. Note 9: Crosstalk rejection is tested by applying a test tone to one channel and holding the other channel at DC level. Crosstalk is measured by calculating the power ratio of the fundamental of each channel's FFT. Note 10:Amplitude matching is measured by applying the same signal to each channel and comparing the magnitude of the fundamental of the calculated FFT. Note 11:Phase matching is measured by applying the same signal to each channel and comparing the phase of the fundamental of the calculated FFT. The data from both ADC channels must be captured simultaneously during this test.
6
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Dual 8-Bit, 40Msps, 3V, Low-Power ADC with Internal Reference and Multiplexed Parallel Outputs MAX1196
Typical Operating Characteristics
(VDD = OVDD = 3V, VREFIN = 2.048V, differential input at -1dB FS, fCLK = 40MHz, CL 10pF, TA = +25C, unless otherwise noted.)
FFT PLOT CHA FFT PLOT CHB FFT PLOT CHA (DIFFERENTIAL INPUT, 8192-POINT DATA RECORD) (DIFFERENTIAL INPUT, 8192-POINT DATA RECORD) (DIFFERENTIAL INPUT, 8192-POINT DATA RECORD)
MAX1196-01 MAX1196-02
-10 -20 AMPLITUDE (dB) -30 -40 -50 HD2 -60 -70 -80 -90 0 2 4 6 8 HD3 fINA
AMPLITUDE (dB)
-40 -50 -60 -70 -80 -90 fINA HD2 HD3
AMPLITUDE (dB)
fCLK = 40.0005678MHz fINA = 1.958036MHz fINB = 7.534287MHz AINA = AINB = -1dB FS COHERENT SAMPLING
-10 -20 -30 fINB
fCLK = 40.0005678MHz fINA = 1.958036MHz fINB = 7.534287MHz AINA = AINB = -1dB FS COHERENT SAMPLING
-10 -20 -30 -40 -50 -60 -70 -80 -90
fINA
fCLK = 40.0005678MHz fINA = 7.534287MHz fINB = 1.958036MHz AINA = AINB = -1dB FS COHERENT SAMPLING
fINB
fINB
HD2
HD3
10 12 14 16 18 20
0
2
4
6
8
10 12 14 16 18 20
0
2
4
6
8
10 12 14 16 18 20
ANALOG INPUT FREQUENCY (MHz)
ANALOG INPUT FREQUENCY (MHz)
ANALOG INPUT FREQUENCY (MHz)
FFT PLOT CHB FFT PLOT CHA FFT PLOT CHB (DIFFERENTIAL INPUT, 8192-POINT DATA RECORD) (DIFFERENTIAL INPUT, 8192-POINT DATA RECORD) (DIFFERENTIAL INPUT, 8192-POINT DATA RECORD)
MAX1196-04 MAX1196-05
-10 -20 AMPLITUDE (dB) -30 -40 -50 HD3 -60 -70 -80 -90 0 2 4 6 8 HD2 fINB
AMPLITUDE (dB)
-40 -50 -60 -70 -80 -90 HD2 fINB
fINA
AMPLITUDE (dB)
fCLK = 40.0005678MHz fINA = 7.534287MHz fINB = 1.958036MHz AINA = AINB = -1dB FS COHERENT SAMPLING
-10 -20 -30
fCLK = 40.0005678MHz fINA = 19.88798MHz fINB = 40.49374MHz AINA = AINB = -1dB FS COHERENT SAMPLING
-10 -20 -30 -40 -50 HD2 -60 -70 -80 -90 HD3 fINB
fCLK = 40.0005678MHz fINA = 19.88798MHz fINB = 40.49374MHz AINA = AINB = -1dB FS COHERENT SAMPLING
fINA
HD3
fINA
10 12 14 16 18 20
0
2
4
6
8
10 12 14 16 18 20
0
2
4
6
8
10 12 14 16 18 20
ANALOG INPUT FREQUENCY (MHz)
ANALOG INPUT FREQUENCY (MHz)
ANALOG INPUT FREQUENCY (MHz)
TWO-TONE IMD PLOT FFT PLOT CHA FFT PLOT CHB (DIFFERENTIAL INPUT, 8192-POINT DATA RECORD) (DIFFERENTIAL INPUT, 8192-POINT DATA RECORD) (DIFFERENTIAL INPUT, 8192-POINT DATA RECORD)
MAX1196-07
-10 -20 AMPLITUDE (dB) -30 -40 -50 -60 -70 -80 -90 0 2 4 6 8 HD2 HD3 fINA
AMPLITUDE (dB)
-30 -40 -50 -60 -70 -80 -90
fINB fINA HD2 HD3
AMPLITUDE (dB)
fCLK = 40.0005678MHz fINA = 40.49374MHz fINB = 19.88798MHz AINA = AINB = -1dB FS COHERENT SAMPLING
-10 -20
fCLK = 40.0005678MHz fINA = 40.49374MHz fINB = 19.88798MHz AINA = AINB = -1dB FS COHERENT SAMPLING
MAX1196-08
-10 -20 -30 -40 -50 -60 -70 -80 -90 fIN1 fIN2
fCLK = 40.001536MHz fINA = 1.997147MHz fINB = 2.045977MHz AIN = -7dB FS COHERENT SAMPLING
fINB
10 12 14 16 18 20
0
2
4
6
8
10 12 14 16 18 20
0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 ANALOG INPUT FREQUENCY (MHz)
ANALOG INPUT FREQUENCY (MHz)
ANALOG INPUT FREQUENCY (MHz)
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MAX1196-09
0
0
0
MAX1196-06
0
0
0
MAX1196-03
0
0
0
7
Dual 8-Bit, 40Msps, 3V, Low-Power ADC with Internal Reference and Multiplexed Parallel Outputs MAX1196
Typical Operating Characteristics (continued)
(VDD = OVDD = 3V, VREFIN = 2.048V, differential input at -1dB FS, fCLK = 40MHz, CL 10pF, TA = +25C, unless otherwise noted.)
TWO-TONE IMD PLOT (DIFFERENTIAL INPUT, 8192-POINT DATA RECORD)
MAX1196-10
SIGNAL-TO-NOISE RATIO vs. ANALOG INPUT FREQUENCY
MAX1196-11
SIGNAL-TO-NOISE + DISTORTION vs. ANALOG INPUT FREQUENCY
CHB 49 48 SINAD (dB)
MAX1196-12
0 -10 -20 AMPLITUDE (dB) -30 -40 -50 -60 -70 -80 -90 7 8 9 10 11 12 fIN1 fIN2 fCLK = 40.001536MHz fIN1 = 9.95643MHz fIN2 = 10.024799MHz AIN = -7dB FS COHERENT SAMPLING
50 CHB 49 48 SNR (dB) 47 46 45 44 0 40 80 120 160
50
47 46 45 44 43 CHA
CHA
13
200
0
40
80
120
160
200
ANALOG INPUT FREQUENCY (MHz)
ANALOG INPUT FREQUENCY (MHz)
ANALOG INPUT FREQUENCY (MHz)
TOTAL HARMONIC DISTORTION vs. ANALOG INPUT FREQUENCY
MAX1196-13
SPURIOUS-FREE DYNAMIC RANGE vs. ANALOG INPUT FREQUENCY
MAX1196-14
FULL-POWER INPUT BANDWIDTH vs. ANALOG INPUT FREQUENCY, DIFFERENTIAL
MAX1196-15
-38
90
2 1 0 GAIN (dB) -1 -2
-48 CHA THD (dBc) -58 SFDR (dBc)
80
CHB
70
-68 CHB -78
60
CHA
50
-3 -4 1 10 100 1000 ANALOG INPUT FREQUENCY (MHz)
-88 0 40 80 120 160 200 ANALOG INPUT FREQUENCY (MHz)
40 0 40 80 120 160 200 ANALOG INPUT FREQUENCY (MHz)
SMALL-SIGNAL INPUT BANDWIDTH vs. ANALOG INPUT FREQUENCY, DIFFERENTIAL
MAX1196-16
SIGNAL-TO-NOISE RATIO vs. INPUT POWER (fIN = 19.88798MHz)
MAX1196-17
SIGNAL-TO-NOISE + DISTORTION vs. INPUT POWER (fIN = 19.88798MHz)
MAX1196-18
2 VIN = 100mVP-P 1 0 GAIN (dB)
55 50 45 40 35 30 25
55 50 45 SINAD (dB) 40 35 30 25
-1 -2 -3 -4 1 10 100 1000 ANALOG INPUT FREQUENCY (MHz)
SNR (dB)
-20
-16
-12
-8
-4
0
-20
-16
-12
-8
-4
0
INPUT POWER (dB FS)
INPUT POWER (dB FS)
8
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Dual 8-Bit, 40Msps, 3V, Low-Power ADC with Internal Reference and Multiplexed Parallel Outputs MAX1196
Typical Operating Characteristics (continued)
(VDD = OVDD = 3V, VREFIN = 2.048V, differential input at -1dB FS, fCLK = 40MHz, CL 10pF, TA = +25C, unless otherwise noted.)
TOTAL HARMONIC DISTORTION vs. INPUT POWER (fIN = 19.88798MHz)
MAX1196-19
SPURIOUS-FREE DYNAMIC RANGE vs. INPUT POWER (fIN = 19.88798MHz)
MAX1196-20
SNR/SINAD, THD/SFDR vs. CLOCK DUTY CYCLE
fINA/B = 7.534287MHz SNR/SINAD, THD/SFDR (dB, dBc) 70 THD 60 SNR 50 SFDR
MAX1196-21
-45 -50 -55 -60 -65 -70 -75 -20 -16 -12 -8 -4
72 67 62 SFDR (dBc) 57 52 47 42
80
SINAD (dBc)
40
SINAD
30 -20 -16 -12 -8 -4 0 40 44 48 52 56 60 INPUT POWER (dB FS) CLOCK DUTY CYCLE (%)
0
INPUT POWER (dB FS)
INTEGRAL NONLINEARITY (131,072-POINT DATA RECORD)
MAX1196-22
DIFFERENTIAL NONLINEARITY (131,072-POINT DATA RECORD)
0.4 0.3 0.2 DNL (LSB) 0.1 0 -0.1 -0.2 -0.3 -0.4 -0.5 fIN = 7.534287MHz
MAX1196-23
0.5 0.4 0.3 0.2 INL (LSB) 0.1 0 -0.1 -0.2 -0.3 -0.4 -0.5 0 32 64 96 fIN = 7.534287MHz
0.5
128 160 192 224 256
0
32
64
96
128 160 192 224 256
DIGITAL OUTPUT CODE
DIGITAL OUTPUT CODE
GAIN ERROR vs. TEMPERATURE, EXTERNAL REFERENCE VREFIN = 2.048V
MAX1196-24
OFFSET ERROR vs. TEMPERATURE, EXTERNAL REFERENCE VREFIN = 2.048V
MAX1196-25
0.5 0.4 GAIN ERROR (%FS) 0.3 0.2 0.1 0 -0.1 -40 -15 10 35 60 CHA CHB
0.2
0 OFFSET ERROR (%FS)
CHA
-0.2
-0.4 CHB -0.6
-0.8 85 -40 -15 10 35 60 85 TEMPERATURE (C) TEMPERATURE (C)
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9
Dual 8-Bit, 40Msps, 3V, Low-Power ADC with Internal Reference and Multiplexed Parallel Outputs MAX1196
Typical Operating Characteristics (continued)
(VDD = OVDD = 3V, VREFIN = 2.048V, differential input at -1dB FS, fCLK = 40MHz, CL 10pF, TA = +25C, unless otherwise noted.)
ANALOG SUPPLY CURRENT vs. TEMPERATURE
MAX1196-26
DIGITAL SUPPLY CURRENT vs. ANALOG INPUT FREQUENCY
MAX1196-27
INTERNAL REFERENCE VOLTAGE vs. ANALOG SUPPLY VOLTAGE
MAX1196-28
33 32 31
8
2.0324 2.0320 2.0316
7 VREFOUT (V)
IOVDD (mA)
IVDD (mA)
30 29 28 27
6
2.0312 2.0308
5
4 26 25 -40 -15 10 35 60 85 TEMPERATURE (C) 3 0 4 8 12 16 20 ANALOG INPUT FREQUENCY (MHz)
2.0304 2.0300 2.70 2.85 3.00 3.15 VDD (V) 3.30 3.45 3.60
INTERNAL REFERENCE VOLTAGE vs. TEMPERATURE
MAX1196-29
SNR/SINAD, THD/SFDR vs. SAMPLING SPEED
80 SNR/SINAD, THD/SFDR (dB, dBc) 60 40 20 0 -20 -40 -60 -80 THD SINAD SNR SFDR fIN = 20MHz
MAX1196-30
2.040
100
2.036 VREFOUT (V)
2.032
2.028
2.024
2.020 -40 -15 10 35 60 85 TEMPERATURE (C)
-100 0 10 20 30 40 50 60 SAMPLING SPEED (Msps)
Pin Description
PIN 1 2, 6, 11, 14, 15 3, 7, 10, 13, 16 4 5 8 9 12 NAME COM VDD GND INA+ INAINBINB+ CLK FUNCTION Common-Mode Voltage Input/Output. Bypass to GND with a 0.1F capacitor. Analog Supply Voltage. Bypass to GND with a capacitor combination of 2.2F in parallel with 0.1F. Analog Ground Channel `A' Positive Analog Input. For single-ended operation, connect signal source to INA+. Channel `A' Negative Analog Input. For single-ended operation, connect INA- to COM. Channel `B' Negative Analog Input. For single-ended operation, connect INB- to COM. Channel `B' Positive Analog Input. For single-ended operation, connect signal source to INB+. Converter Clock Input
10
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Dual 8-Bit, 40Msps, 3V, Low-Power ADC with Internal Reference and Multiplexed Parallel Outputs
Pin Description (continued)
PIN 17 NAME T/B T/B selects the ADC digital output format. High: Two's complement. Low: Straight offset binary. Sleep Mode Input. High: Deactivates the two ADCs, but leaves the reference bias circuit active. Low: Normal operation. High-Active Power-Down Input. High: Power-down mode Low: Normal operation Low-Active Output Enable Input. High: Digital outputs disabled Low: Digital outputs enabled No Connection. Do not connect. A/B Data Indicator. This digital output indicates CHA data (A/B = 1) or CHB data (A/B = 0) to be present on the output. A/B follows the external clock signal with typically 6ns delay. Output-Driver Ground Output-Driver Supply Voltage. Bypass to OGND with a capacitor combination of 2.2F in parallel with 0.1F. Three-State Digital Output, Bit 0. Depending on status of A/B, output data reflects channel A or channel B data. Three-State Digital Output, Bit 1. Depending on status of A/B, output data reflects channel A or channel B data. Three-State Digital Output, Bit 2. Depending on status of A/B, output data reflects channel A or channel B data. Three-State Digital Output, Bit 3. Depending on status of A/B, output data reflects channel A or channel B data. Three-State Digital Output, Bit 4. Depending on status of A/B, output data reflects channel A or channel B data. Three-State Digital Output, Bit 5. Depending on status of A/B, output data reflects channel A or channel B data. Three-State Digital Output, Bit 6. Depending on status of A/B, output data reflects channel A or channel B data. Three-State Digital Output, Bit 7 (MSB). Depending on status of A/B, output data reflects channel A or channel B data. Reference Input. VREFIN = 2 x (VREFP - VREFN). Bypass to GND with a 0.1F capacitor. Positive Reference I/O. Conversion range is (VREFP - VREFN). Bypass to GND with a 0.1F capacitor. Negative Reference I/O. Conversion range is (VREFP - VREFN). Bypass to GND with a 0.1F capacitor. FUNCTION
MAX1196
18
SLEEP
19
PD
20 21-29, 35, 36 30 31, 34 32, 33 37 38 39 40 41 42 43 44 45 46 47 48
OE N.C. A/B OGND OVDD D0A/B D1A/B D2A/B D3A/B D4A/B D5A/B D6A/B D7A/B
REFOUT Internal Reference Voltage Output. Can be connected to REFIN through a resistor or a resistor-divider. REFIN REFP REFN
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11
Dual 8-Bit, 40Msps, 3V, Low-Power ADC with Internal Reference and Multiplexed Parallel Outputs MAX1196
2-BIT FLASH ADC STAGE 1 STAGE 2 STAGE 6 STAGE 7 STAGE 1 STAGE 2 STAGE 6 2-BIT FLASH ADC STAGE 7
DIGITAL ALIGNMENT LOGIC T/H 8 T/H
DIGITAL ALIGNMENT LOGIC 8
VINA
VINB OUTPUT MULTIPLEXER 8 D0A/B-D7A/B
Figure 1. Pipelined Architecture--Stage Blocks
Detailed Description
The MAX1196 uses a 7-stage, fully differential, pipelined architecture (Figure 1) that allows for high-speed conversion while minimizing power consumption. Samples taken at the inputs move progressively through the pipeline stages every half clock cycle. Including the delay through the output latch, the total clock-cycle latency is 5 clock cycles for CHA and 5.5 clock cycles for CHB. Flash ADCs convert the held input voltages into a digital code. Internal MDACs convert the digitized results back into analog voltages, which are then subtracted from the original held input signals. The resulting error signals are then multiplied by two, and the residues are passed along to the next pipeline stages where the process is repeated until the signals have been processed by all 7 stages. Both input channels are sampled on the rising edge of the clock and the resulting data is multiplexed at the output. CHA data is updated on the rising edge (5 clock cycles later) and CHB data is updated on the falling edge (5.5 clock cycles later) of the clock signal. The A/B indicator follows the clock signal with a typical delay time of 6ns and remains high when CHA data is updated and low when CHB data is updated.
S4b, S5a, and S5b are closed. The fully differential circuits sample the input signals onto the two capacitors (C2a and C2b) through switches S4a and S4b. S2a and S2b set the common mode for the amplifier input, and open simultaneously with S1, sampling the input waveform. Switches S4a, S4b, S5a, and S5b are then opened before switches S3a and S3b connect capacitors C1a and C1b to the output of the amplifier and switch S4c is closed. The resulting differential voltages are held on capacitors C2a and C2b. The amplifiers are used to charge capacitors C1a and C1b to the same values originally held on C2a and C2b. These values are then presented to the first stage quantizers and isolate the pipelines from the fast-changing inputs. The wide input bandwidth T/H amplifiers allow the MAX1196 to track and sample/hold analog inputs of high frequencies (>Nyquist). Both ADC inputs (INA+, INB+, INA-, and INB-) can be driven either differentially or single ended. Match the impedance of INA+ and INA-, as well as INB+ and INB-, and set the common-mode voltage to midsupply (VDD/2) for optimum performance.
Analog Inputs and Reference Configurations
The full-scale range of the MAX1196 is determined by the internally generated voltage difference between REFP (VDD/2 + VREFIN/4) and REFN (VDD/2 - VREFIN/4). The full-scale range for both on-chip ADCs is adjustable through the REFIN pin, which is provided for this purpose.
Input Track-and-Hold (T/H) Circuits
Figure 2 displays a simplified functional diagram of the input track-and-hold (T/H) circuits in both track and hold mode. In track mode, switches S1, S2a, S2b, S4a,
12
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Dual 8-Bit, 40Msps, 3V, Low-Power ADC with Internal Reference and Multiplexed Parallel Outputs MAX1196
INTERNAL BIAS S2a C1a S4a INA+ C2a S4c S1 OUT S4b C2b C1b S3b S2b INTERNAL BIAS INTERNAL BIAS S2a C1a S4a INB+ C2a S4c S1 OUT S4b C2b C1b S3b S2b INTERNAL BIAS S5b COM OUT S5b COM HOLD TRACK HOLD TRACK CLK INTERNAL NONOVERLAPPING CLOCK SIGNALS OUT COM S5a S3a
INA-
COM S5a S3a
MAX1196
INB-
Figure 2. MAX1196 T/H Amplifiers
The MAX1196 provides three modes of reference operation: * Internal reference mode * Buffered external reference mode * Unbuffered external reference mode In internal reference mode, connect the internal reference output REFOUT to REFIN through a resistor (e.g.,
10k) or resistor-divider, if an application requires a reduced full-scale range. For stability and noise-filtering purposes, bypass REFIN with a 0.1F capacitor to GND. In internal reference mode, REFOUT, COM, REFP, and REFN become low-impedance outputs. In buffered external reference mode, adjust the reference voltage levels externally by applying a stable and accurate voltage at REFIN. In this mode, COM, REFP,
13
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Dual 8-Bit, 40Msps, 3V, Low-Power ADC with Internal Reference and Multiplexed Parallel Outputs
and REFN are outputs. REFOUT can be left open or connected to REFIN through a >10k resistor. In unbuffered external reference mode, connect REFIN to GND. This deactivates the on-chip reference buffers for REFP, COM, and REFN. With their buffers shut down, these nodes become high-impedance inputs and can be driven through separate, external reference sources. For detailed circuit suggestions and how to drive this dual ADC in buffered/unbuffered external reference mode, see the Applications Information section.
MAX1196
Clock jitter is especially critical for undersampling applications. The clock input should always be considered as an analog input and routed away from any analog input or other digital signal lines. The MAX1196 clock input operates with a voltage threshold set to VDD/2. Clock inputs with a duty cycle other than 50%, must meet the specifications for high and low periods as stated in the Electrical Characteristics.
System Timing Requirements
Figure 3 shows the relationship between clock and analog input, A/B indicator, and the resulting valid CHA/CHB data output. CHA and CHB data are sampled on the rising edge of the clock signal. Following the rising edge of the 5th clock cycles, the digitized value of the original CHA sample is presented at the output, followed one-half clock cycle later by the digitized value of the original CHB sample. A channel selection signal (A/B indicator) allows the user to determine which output data represents which input channel. With A/B = 1, digitized data from CHA is present at the output and with A/B = 0 digitized data from CHB is present.
Clock Input (CLK)
The MAX1196's CLK input accepts CMOS-compatible clock signal. Since the interstage conversion of the device depends on the repeatability of the rising and falling edges of the external clock, use a clock with low jitter and fast rise and fall times (<2ns). In particular, sampling occurs on the rising edge of the clock signal, requiring this edge to provide lowest possible jitter. Any significant aperture jitter would limit the SNR performance of the on-chip ADCs as follows: 1 SNR = 20 x log 2 x x fIN x t AJ where fIN represents the analog input frequency and tAJ is the time of the aperture jitter.
5 CLOCK-CYCLE LATENCY (CHA), 5.5 CLOCK-CYCLE LATENCY (CHB)
CHA
CHB
tCLK tCL CLK tCH
tDOB A/B tDA/B D0A/B-D7A/B D0B D1A CHB CHA
tDOA CHB CHA CHB CHA CHB CHA CHB CHA CHB CHA CHB
D1B
D2A
D2B
D3A
D3B
D4A
D4B
D5A
D5B
D6A
D6B
Figure 3. System Timing Diagram 14 ______________________________________________________________________________________
Dual 8-Bit, 40Msps, 3V, Low-Power ADC with Internal Reference and Multiplexed Parallel Outputs MAX1196
Digital Output Data, Output Data Format Selection (T/B), Output Enable (OE), Channel Selection (A/B)
All digital outputs, D0A/B-D7A/B (CHA or CHB data) and A/B are TTL/CMOS-logic compatible. The output coding can be chosen to be either offset binary or two's complement (Table 1) controlled by a single pin (T/B). Pull T/B low to select offset binary and high to activate two's complement output coding. The capacitive load on the digital outputs D0A/B-D7A/B should be kept as low as possible (<15pF), to avoid large digital currents that could feed back into the analog portion of the MAX1196, thereby degrading its dynamic performance. Using buffers on the digital outputs of the ADCs can further isolate the digital outputs from heavy capacitive loads. To further improve the dynamic performance of the MAX1196, small-series resistors (e.g., 100) can be added to the digital output paths, close to the MAX1196. Figure 4 displays the timing relationship between output enable and data output valid as well as powerdown/wake-up and data output valid.
Power-Down (PD) and Sleep (SLEEP) Modes
The MAX1196 offers two power-save modes--sleep and full power-down mode. In sleep mode (SLEEP = 1), only the reference bias circuit is active (both ADCs are disabled), and current consumption is reduced to 3mA. To enter full power-down mode, pull PD high. With OE simultaneously low, all outputs are latched at the last value prior to the power down. Pulling OE high forces the digital outputs into a high-impedance state.
Applications Information
Figure 5 depicts a typical application circuit containing two single-ended-to-differential converters. The internal reference provides a VDD/2 output voltage for level-shifting purposes. The input is buffered and then split to a voltage follower and inverter. One lowpass filter per amplifier suppresses some of the wideband noise associated with high-speed operational amplifiers. The user can select the RISO and CIN values to optimize the filter performance, to suit a particular application. For the application in Figure 5, an RISO of 50 is placed before the capacitive load to prevent ringing and oscillation. The 22pF CIN capacitor acts as a small filter capacitor.
OE
Using Transformer Coupling
tENABLE tDISABLE HIGH-Z
OUTPUT D0A/B-D7A/B
HIGH-Z
VALID DATA
Figure 4. Output Timing Diagram
An RF transformer (Figure 6) provides an excellent solution to convert a single-ended source signal to a fully differential signal, required by the MAX1196 for optimum performance. Connecting the center tap of the transformer to COM provides a VDD/2 DC level shift to the input. Although a 1:1 transformer is shown, a step-up transformer can be selected to reduce the drive requirements. A reduced signal swing from the input driver, such as an op amp, can also improve the overall distortion.
Table 1. MAX1196 Output Codes for Differential Inputs
DIFFERENTIAL INPUT VOLTAGE* VREF x 255/256 VREF x 1/256 0 -VREF x 1/256 -VREF x 255/256 -VREF x 256/256 DIFFERENTIAL INPUT +Full Scale - 1LSB +1LSB Bipolar Zero -1LSB -Full Scale + 1LSB -Full Scale STRAIGHT OFFSET BINARY T/B = 0 1111 1111 1000 0001 1000 0000 0111 1111 0000 0001 0000 0000 TWO'S COMPLEMENT T/B = 1 0111 1111 0000 0001 0000 0000 1111 1111 1000 0001 1000 0000
*VREF = VREFP - VREFN ______________________________________________________________________________________ 15
Dual 8-Bit, 40Msps, 3V, Low-Power ADC with Internal Reference and Multiplexed Parallel Outputs MAX1196
+5V
0.1F LOWPASS FILTER MAX4108 300 0.1F INARIS0 50 CIN 22pF
-5V
0.1F
600 +5V 300
600
COM 0.1F 0.1F INPUT MAX4108 300 0.1F MAX4108 INA+ RIS0 50 0.1F CIN 22pF 600 0.1F LOWPASS FILTER +5V
-5V
300 -5V
300 300 +5V 600
MAX1196
0.1F LOWPASS FILTER MAX4108 300 0.1F INBRIS0 50 CIN 22pF
-5V
0.1F
+5V 300 0.1F INPUT MAX4108 300 0.1F 0.1F
600
600
+5V 600 0.1F MAX4108 RIS0 50 -5V 0.1F CIN 22pF LOWPASS FILTER INB+
-5V
300
300 300 600
Figure 5. Typical Application for Single-Ended-to-Differential Conversion 16 ______________________________________________________________________________________
Dual 8-Bit, 40Msps, 3V, Low-Power ADC with Internal Reference and Multiplexed Parallel Outputs
In general, the MAX1196 provides better SFDR and THD with fully differential input signals than singleended drive, especially for very high input frequencies. In differential input mode, even-order harmonics are lower as both inputs (INA+, INA- and/or INB+, INB-) are balanced, and each of the ADC inputs only requires half the signal swing compared to single-ended mode.
Buffered External Reference Drives Multiple ADCs
Multiple-converter systems based on the MAX1196 are well suited for use with a common reference voltage. The REFIN pin of those converters can be connected directly to an external reference source. A precision bandgap reference like the MAX6062 generates an external DC level of 2.048V (Figure 8), and exhibits a noise voltage density of 150nV/Hz. Its output passes through a one-pole lowpass filter (with 10Hz cutoff frequency) to the MAX4250, which buffers the reference before its output is applied to a second 10Hz lowpass filter. The MAX4250 provides a low offset voltage (for high gain accuracy) and a low noise level. The passive 10Hz filter following the buffer attenuates noise
MAX1196
Single-Ended AC-Coupled Input Signal
Figure 7 shows an AC-coupled, single-ended application. Amplifiers like the MAX4108 provide high speed, high bandwidth, low noise, and low distortion to maintain the integrity of the input signal.
25 INA+ 22pF VIN 0.1F VIN N.C. 1 2 3 T1 6 5 4 2.2F 0.1F MAX4108 100 COM 0.1F
REFP
1k
RISO 50 INA+ CIN 22pF
1k
COM REFN 0.1F RISO 50
MINICIRCUITS TT1-6-KK81 25 INA22pF MAX1196 25 INB+ 22pF VIN 0.1F VIN N.C. 1 2 3 T1 6 5 4 2.2F 0.1F REFN MAX4108 100 1k 0.1F 1k REFP 100
INACIN 22pF
MAX1196
RISO 50 INB+ CIN 22pF
MINICIRCUITS TT1-6-KK81 25 INB22pF 100
0.1F RISO 50 INBCIN 22pF
Figure 6. Transformer-Coupled Input Drive
Figure 7. Using an Op Amp for Single-Ended, AC-Coupled Input Drive
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17
Dual 8-Bit, 40Msps, 3V, Low-Power ADC with Internal Reference and Multiplexed Parallel Outputs MAX1196
3.3V 0.1F 0.1F 1 0.1F MAX6062 2 16.2k 3 5 MAX4250 4 3 10Hz LOWPASS FILTER 2 1 162 100F 0.1F 0.1F 0.1F 10Hz LOWPASS FILTER 3.3V 2.048V N.C. 29 31 32 1 2 REFOUT REFIN REFP REFN COM
N=1 MAX1196
1F
NOTE: ONE FRONT-END REFERENCE CIRCUIT DESIGN CAN BE USED WITH UP TO 1000 ADCs.
0.1F
2.2F 10V
N.C.
29 31
REFOUT REFIN REFP REFN COM
0.1F
32 1 2
N = 1000 MAX1196
0.1F 0.1F 0.1F
Figure 8. External Buffered (MAX4250) Reference Drive Using a MAX6062 Bandgap Reference
produced in the voltage-reference and buffer stages. This filtered noise density, which decreases for higher frequencies, meets the noise levels specified for precision-ADC operation.
Unbuffered External Reference Drives Multiple ADCs
Connecting each REFIN to analog ground disables the internal reference of each device, allowing the internal reference ladders to be driven directly by a set of external reference sources. Followed by a 10Hz lowpass filter and precision voltage-divider, the MAX6066 generates a DC level of 2.500V. The buffered outputs of this divider are set to 2.0V, 1.5V, and 1.0V, with an accuracy that depends on the tolerance of the divider resistors. Those three voltages are buffered by the MAX4252, which provides low noise and low DC offset. The individ18
ual voltage followers are connected to 10Hz lowpass filters, which filter both the reference-voltage and amplifier noise to a level of 3nV/Hz. The 2.0V and 1.0V reference voltages set the differential full-scale range of the associated ADCs at 2VP-P. The 2.0V and 1.0V buffers drive the ADCs' internal ladder resistances between them. Note that the common power supply for all active components removes any concern regarding power-supply sequencing when powering up or down. With the outputs of the MAX4252 matching better than 0.1%, the buffers and subsequent lowpass filters can be replicated to support as many as 32 ADCs. For applications requiring more than 32 matched ADCs, a voltage-reference and divider string common to all converters is highly recommended.
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Dual 8-Bit, 40Msps, 3V, Low-Power ADC with Internal Reference and Multiplexed Parallel Outputs MAX1196
3.3V 0.1F 1 2.0V MAX6066 2 21.5k 3 4 1/4 MAX4252 1 2 3 21.5k 1.5V 5 4 1/4 MAX4252 7 6 1F 21.5k 3.3V 0.1F 11 10F 6V 1.47k 3.3V 10 4 1/4 MAX4252 8 21.5k MAX4254 POWER-SUPPLY BYPASSING. PLACE CAPACITOR AS CLOSE AS POSSIBLE TO THE OP AMP. 9 11 21.5k 10F 6V 1.47k 330F 6V N.C. 29 31 32 1 2 REFOUT REFIN REFP REFN COM 1.0V AT -8mA 47k 330F 6V 0.1F 2.2F 10V 47k 11 10F 6V 1.47k 3.3V 1.5V AT 0mA 330F 6V 0.1F 0.1F 0.1F 47k 2 COM 3.3V 2.0V AT 8mA N.C. 29 31 32 1
REFOUT REFIN REFP REFN
N=1 MAX1196
1.0V
N = 32 MAX1196
NOTE: ONE FRONT-END REFERENCE CIRCUIT DESIGN CAN BE USED WITH UP TO 32 ADCs.
0.1F 0.1F 0.1F
Figure 9. External Unbuffered Reference Drive With MAX4252 and MAX6066
Typical QAM Demodulation Application
A frequently used modulation technique in digital communications applications is quadrature amplitude modulation (QAM). Typically found in spread- spectrumbased systems, a QAM signal represents a carrier frequency modulated in both amplitude and phase. At the transmitter, modulating the baseband signal with quadrature outputs, a local oscillator followed by subsequent up-conversion can generate the QAM signal. The result is an in-phase (I) and a quadrature (Q) carrier
component, where the Q component is 90 degrees phase-shifted with respect to the in-phase component. At the receiver, the QAM signal is divided down into its I and Q components, essentially representing the modulation process reversed. Figure 10 displays the demodulation process performed in the analog domain, using the dual matched 3V, 8-bit ADC MAX1196, and the MAX2451 quadrature demodulator to recover and digitize the I and Q baseband signals. Before being digitized by the MAX1196, the mixed-down signal components can be filtered by matched analog filters, such
19
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Dual 8-Bit, 40Msps, 3V, Low-Power ADC with Internal Reference and Multiplexed Parallel Outputs MAX1196
A/B
MAX2451
INA+ INA0 90
MAX1196 INB+ INB-
DSP POSTPROCESSING
DOWNCONVERTER /8
CHA AND CHB DATA ALTERNATINGLY AVAILABLE ON 8-BIT MULTIPLEXED OUTPUT BUS.
Figure 10. Typical QAM Application Using the MAX1196
as Nyquist or pulse-shaping filters, which remove unwanted images from the mixing process, thereby enhancing the overall signal-to-noise (SNR) performance and minimizing intersymbol interference.
Grounding, Bypassing, and Board Layout
The MAX1196 requires high-speed board layout design techniques. Locate all bypass capacitors as close to the device as possible, preferably on the same side as the ADC, using surface-mount devices for minimum inductance. Bypass VDD, REFP, REFN, and COM with two parallel 0.1F ceramic capacitors and a 2.2F bipolar capacitor to GND. Follow the same rules to bypass the digital supply (OVDD) to OGND. Multilayer boards with separated ground and power planes produce the highest level of signal integrity. Consider the use of a split ground plane arranged to match the physical location of the analog ground (GND) and the digital output-driver ground (OGND) on the ADC's package. The two ground planes should be joined at a single point such that the noisy digital ground currents do not interfere with the analog ground plane. The ideal location of this connection can be determined experimentally at a point along the gap between the two ground planes, which produces optimum results. Make this connection with a low-value, surface-mount resistor (1 to 5), a ferrite bead, or a direct short. Alternatively, all ground pins could share the same ground plane, if the ground plane is sufficiently isolated from any noisy, digital systems ground plane (e.g., downstream output buffer or DSP ground plane). Route
20
high-speed digital signal traces away from the sensitive analog traces of either channel. Make sure to isolate the analog input lines to each respective converter to minimize channel-to-channel crosstalk. Keep all signal lines short and free of 90 degree turns.
Static Parameter Definitions
Integral Nonlinearity (INL)
Integral nonlinearity is the deviation of the values on an actual transfer function from a straight line. This straight line can be either a best-straight-line fit or a line drawn between the endpoints of the transfer function, once offset and gain errors have been nullified. The static linearity parameters for the MAX1196 are measured using the best-straight-line fit method.
Differential Nonlinearity (DNL)
Differential nonlinearity is the difference between an actual step width and the ideal value of 1LSB. A DNL error specification of less than 1LSB guarantees no missing codes and a monotonic transfer function.
Dynamic Parameter Definitions
Aperture Jitter
Figure 11 depicts the aperture jitter (tAJ), which is the sample-to-sample variation in the aperture delay.
Aperture Delay
Aperture delay (tAD) is the time defined between the rising edge of the sampling clock and the instant when an actual sample is taken (Figure 11).
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Dual 8-Bit, 40Msps, 3V, Low-Power ADC with Internal Reference and Multiplexed Parallel Outputs
Total Harmonic Distortion (THD)
CLK
MAX1196
THD is typically the ratio of the RMS sum of the first four harmonics of the input signal to the fundamental itself. This is expressed as: V2 2 + V3 2 + V4 2 + V5 2 THD = 20 x log V1
ANALOG INPUT tAD tAJ SAMPLED DATA (T/H)
where V1 is the fundamental amplitude, and V2 through V5 are the amplitudes of the 2nd- through 5th-order harmonics.
TRACK HOLD TRACK
T/H
Spurious-Free Dynamic Range (SFDR)
SFDR is the ratio expressed in decibels of the RMS amplitude of the fundamental (maximum signal component) to the RMS value of the next largest spurious component, excluding DC offset.
Figure 11. T/H Aperture Timing
Signal-to-Noise Ratio (SNR)
For a waveform perfectly reconstructed from digital samples, the theoretical maximum SNR is the ratio of the full-scale analog input (RMS value) to the RMS quantization error (residual error). The ideal, theoretical minimum analog-to-digital noise is caused by quantization error only and results directly from the ADC's resolution (N bits): SNRdB[max] = 6.02dB x N + 1.76dB In reality, there are other noise sources besides quantization noise: thermal noise, reference noise, clock jitter, etc. SNR is computed by taking the ratio of the RMS signal to the RMS noise, which includes all spectral components minus the fundamental, the first five harmonics, and the DC offset.
Intermodulation Distortion (IMD)
The two-tone IMD is the ratio expressed in decibels of either input tone to the worst third-order (or higher) intermodulation products. The individual input tone levels are at -7dB full scale.
Pin-Compatible Upgrades (Sampling Speed and Resolution)
8-BIT PART N/A MAX1195 MAX1197 MAX1198 N/A MAX1196 10-BIT PART MAX1185 MAX1183 MAX1182 MAX1180 MAX1190 MAX1186 SAMPLING SPEED (Msps) 20 40 60 100 120 40, multiplexed
Signal-to-Noise Plus Distortion (SINAD)
SINAD is computed by taking the ratio of the RMS signal to all spectral components minus the fundamental and the DC offset.
Effective Number of Bits (ENOB)
ENOB specifies the dynamic performance of an ADC at a specific input frequency and sampling rate. An ideal ADC error consists of quantization noise only. ENOB for a full-scale sinusoidal input waveform is computed from: SINAD - 1.76 ENOB = 6.02
Chip Information
TRANSISTOR COUNT: 11,601 PROCESS: CMOS
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21
Dual 8-Bit, 40Msps, 3V, Low-Power ADC with Internal Reference and Multiplexed Parallel Outputs MAX1196
Functional Diagram
VDD GND INA+ T/H INAADC DEC 8 MUX
OGND OVDD
A/B
CLK
CONTROL
8
8
INB+ T/H INBADC DEC
OUTPUT DRIVERS
8
D7B-D0B OR D7A-D0A OE T/B PD SLEEP
REFERENCE
MAX1196
REFOUT REFN COM REFP REFIN
22
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Dual 8-Bit, 40Msps, 3V, Low-Power ADC with Internal Reference and Multiplexed Parallel Outputs
Package Information
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information go to www.maxim-ic.com/packages.)
48L,TQFP.EPS
MAX1196
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 23 (c) 2002 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.

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